1. Field of the Invention
The present invention relates to an asynchronous time division communication system with at least one station including a buffer circuit and associated processing means to write data packets in said buffer circuit at a send clock frequency and to read data packets from said buffer circuit at a receive clock frequency, said processing means being further able to assess the real packet filling level of said buffer circuit and to adjust said receive clock frequency in function of the thus assessed real filling level.
2. Description of the Prior Art
Such a communication system is known in the art, e.g. from the published French patent application No. 2579047. Therein the receive or read clock frequency is directly regulated by means of the assessed real filling level of the buffer circuit, so that the number of regulations performed may be excessively high, especially when in the system the data packets are subjected to stochastic delays as these give rise to frequent changes of the real filling level of the buffer. Such stochastic delays are not taken into account in the known system.